This invention relates generally to a method of making an ultra high density pad array chip carrier and more particularly to a method for making a variety of high density pad array chip carriers from a universal structure.
With the increasing size of large scale integrated circuit chips the number of input and output connections that have to be made to a chip has correspondingly increased. This trend has encouraged the evolution to smaller and more dense leadless chip carriers. Leadless chip carriers generally consist of a package containing a square plate of ceramic such as alumina which forms a substrate or base onto which a chip is mounted. Electrical connection paths within the leadless chip carrier allow the leads of the chip to be brought to external contact pads formed around each of the four sides of the ceramic base of the carrier. The carrier is then surface mounted, usually onto a generally larger printed circuit (PC) board, or other ceramic board simply by placing the carrier on top of the corresponding contact pads, which mirror those contact pads of the chip carrier. An electrical and mechanical connection is then made by soldering the chip carrier to this generally larger board by reflow soldering. This arrangement allows greater density of input and output connections to be achieved.
Disadvantages do, however, arise with leadless chip carriers because of the way in which they are connected to a board. Since the leadless chip carrier is rigidly joined to a generally larger PC board or ceramic board and lacks any ability to accommodate relative movement between the carrier and the board onto which it is mounted, if the chip carrier and board are of materials having different coefficients of thermal expansion, changing in temperature will cost differential expansion of the two components. This induces strain on the solder connections which can cause failure of the electrical and mechanical connection, especially after repeated thermal cycling. However, it is known that small ceramic chip carriers operate more reliably in a thermal cycling environment than larger chip carriers, expecially when these are mounted onto a printed circuit board, therefore it is clear that if the designer seeks to improve the overall reliability of a mounted ceramic chip carrier package, the designer must attempt to reduce the size of the chip carrier.
One known arrangement for a pad array or pad grid array chip carrier utilized thick film techniques to form a pattern of screened-on metallic paste on the surface of an unfired ceramic substrate. Through-holes in this ceramic substrate are filled with a conductive glass-metal paste combination and are connected with electrical conductors formed by the pattern of screened on metallic paste. The ceramic substrate then has a second ceramic layer added beneath it having contact pads on its bottom surface and separated from the conductors and die mount pad on the first ceramic layer. These co-fired pad array carriers use co-fired metallization not only to fill the through-holes but also to form the conductors and die attach area. The size and density realizable for such a co-fired chip carrier, while utilizing the center area beneath the die mount pad, is limited by the additive co-fired process itself in that the narrowest conductor which can be screened is 5 mils or milli-inches with a typical production width being 8 mils wide. Such constraints limit the size and density posssible for a chip carrier manufactured using this co-fired method and they in turn can strain further desired improvements in reliability and in cost. Therefore, a need exists to reduce the use of these expensive co-fired techniques, which necessarily limit the minimum possible size of the chip carrier arrangement and which in turn affect the reliability as well as the per unit cost.
Furthermore, the co-firing process with the conventional pad array design, requires the need to buy a custom punching tool for every new pad array chip carrier design. Often, one punching tool is needed for the top layer, while another one is required for the bottom layer. With this design, as the number of input/output ports changes, the amount of inventory of the resultant customized carriers required to accommodate the different number of ports is high. Therefore, a need exists to standardize the method of making the ultra high density pad array chip carrier while reducing production costs and production time of making an ultra high density pad array chip carrier.